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Product Descriptions

The Allwinner R16 is designed to provide a scalability,low-power capabilities,high performance application processor solution for Internet-of-Things(IoT) applications,which outperforms competitors in the terms of its system performance,great flexibility and energy-efficiency. The processor perfectly supports various applications of mainstream operating systems such as Android,Linux,etc.

R16 packs four ARM CortexTM-A7 CPU cores and Mali400MP2 graphics architecture to support display and gaming effects.Video Engine is included to provide full motion playback of up to 1080p high-definition video encoding/decoding and supports MPEG1/2/4, WMV9/VC1, H.263,H.264, VP8 and JPEG/MJPEG video decoding standards with dedicated hardware.The integration of display subsystem enables high resolution and high color display.Also the CSI controller allows for taking photos, video input and streaming video.

The processor has optimized external memory interfaces to SDRAM, Nand Flash and SD/MMC.The SDRAM port can be configured to support DDR3 and DDR3L. In addition,to reduce total system cost and deliver better architecture scalability,Allwinner’s R16 comes with many extensive connectivity and interfaces,including seven groups of GPIOs,five UARTs,one SPIs,four TWIs,4-lane MIPI DSI,LVDS LCD controller,USB OTG/HOST,

I2S/PCM,RSB,and a lot more.

Allwinner also designed R16 to be extremely power-efficient to realize massive ubiquitous deployment.It achieves lower power consumption with a balanced combination of several features:the exceedingly power efficient CortexTM-A7 CPU cores,the advanced fabrication process,the battery-saving DVFS technology support,and the low power design architectures,etc

Product Features

2.1. CPU Architecture

The quad-core R16 platform is based on ARM’s CortexTM-A7 CPU architecture.

? ARMv7 ISA standard instruction set 

? Thumb-2 

? NEON with SIMD and VFPv4 support 

? Support hardware virtualization 

? Support LPAE 

? Integrated 32KB L1 instruction cache and 32KB L1 data cache for each CPU 

? Shared 512KB L2 cache 

? Support DVFS with independent power domain 

2.2. GPU Architecture 

? ARM Mali400MP2 

? Support OpenGL ES 2.0 / OpenVG 1.1 standard 

2.3. Memory Subsystem 

Boot ROM 

? Support system boot from Raw NAND, eMMC , SPI Nor Flash, SD/TF card 

? Support system code download through USB OTG 

SDRAM 

? Support 2GB address space 

? Support 16-bit bus width 

? Compatible with JEDEC standard DDR3/DDR3L SDRAM 

? Clock frequency up to 667MHz ? Support Memory Dynamic Frequency Scale

 ? Support two ranks 

? Support 16 address signal lines and 3 bank signal lines 

NAND Flash 

? Comply to ONFI 2.3 and Toggle 1.0 

? Up to 64-bit ECC per 512 bytes or 1024 bytes 

? 8-bit Raw NAND flash controller sharing pin with eMMC 

? Up to 2 CE and 2 RB signals 

? Support SLC/MLC/TLC NAND and EF-NAND 

? Support SDR/ONFI DDR/Toggle DDR NAND 

SD/MMC Interface 

? Up to three SD/MMC controllers 

? Comply to eMMC standard specification V4.41, SD physical layer specification V2.0, SDIO card specification V2.0 

? 1-bit or 4-bit data bus transfer mode for SD and SDIO cards up to 50MHz 

? 1-bit,4-bit or 8-bit data bus transfer mode for MMC cards up to 50MHz in SDR modes

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