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Product Descriptions

RKnanoC is a low-cost, low-power, high-efficiency digital multimedia chip which is based on ARM low power processor architecture with hardware accelerator. It is designed for portable audio product applications such as MP3 player etc.

RKnanoC can support decode for various types of audio standards such as MP3/WMA /OGG/FLAG/AAC etc. Because of build-in audio hardware accelerator, RKnanoC can achieve audio decode at a very low system frequency, this can save chip power consumption. By providing a complete set of peripheral interface, RKnanoC can support very flexible applications, including NAND Flash, LCDC, USB OTG, SD/MMC, I2C, I2S, SPI, UART, PWM etc.

Product Features

z System Operation 

? ARM processor 

? AHB-lite bus connection 

? Selectable booting method 

? Boot from NAND FLASH 

? Boot from eMMC flash 

? Boot from SPI NOR flash 

z Memory Organization 

? Internal 224KB SRAM for IRAM and DRAM 

? Embedded 64KB ROM for decoder and system code

z Processor 

? ARM Cortex-M3 low power core 

? A Thumb instruction set subset 

? Banked Stack Pointer (SP) only 

? Hardware divide instructions, SDIV and UDIV (Thumb 32-bit instructions) 

? Handler and Thread modes 

? Thumb and Debug states 

? Interruptible-continued LDM/STM, PUSH/POP for low interrupt latency 

? Automatic processor state saving and restoration for low latency Interrupt Service Routine (ISR) entry and exit 

? Nested Vectored Interrupt Controller (NVIC) 

? 26 external interrupts. 

? 8-level priority of interrupt

z Clock & Power Management 

? One on-chip PLL, system main clock can be PLL clock or OSC input clock 

? Support different main clock and internal AHB Bus clock ratio: 1:1, 1:2, 1:3, 1:4, up to 1:8 modes 

? Support different AHB Bus clock and ARM system tick clock ratio: 1:2, 1:3, 1:4, up to 1:8 modes 

? Support different AHB Bus clock and ARM APB Bus clock ratio: 1:1, 1:2, 1:3 and 1:4 mode 

? 100MHz Max frequency for ARM Core 

? Clock gating for ARM Cortex-M3 sleep mode and other peripherals

? Support ARM clock bypass/divider 2/divider 4 path for 24MHz arm clock

z Hardware Accelerator for MP3 decode 

? MP3 imdct36 calculation module 

? MP3 subband synthesize module

z Memory Interface 

? External-Memory controller 

? Support 4 chip selects for NAND flash 

? Support 24/40/60bits ECC error correction 

? Support 8bits data-width to external NAND 

? SD/MMC controller 

? SD/MMC SPI mode/1bit mode/4bit mode 

? Support Multi Media Card Specification Version 4.41 

? Support SD Memory Card Specification Version 3.0 

? Support Secure Digital I/O(SDIO Version3.0) 

? Cards Clock Rate up to PCLK, Re-scaling the SD/MMC clock (PCLK) with the 8-bits pre-scale register in SCU block

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