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Product Descriptions

RK3399Pro is a low power, high performance processor for computing, personal mobile internet devices and other smart device applications. Based on Big.Little architecture, it integrates dual-core Cortex-A72 and quad-core Cortex-A53 with separate NEON coprocessor.

Equipped with one powerful neural network process unit(NPU), it supports mainstream platforms in the market, such as caffe, tensor flow, and so on.

Many embedded powerful hardware engines provide optimized performance for high-end application. RK3399Pro supports multi-format video decoders and encoders.

Embedded 3D GPU makes RK3399Pro completely compatible with OpenGL ES1.1/2.0/3.0/3.1, OpenCL and DirectX 11.1. Special 2D hardware engine with MMU will maximize display performance and provide very smooth operation.

Product Features

The features listed below which may or may not be present in actual product, may be subject  to the third party licensing requirements. Please contact Rockchip for actual product feature  configurations and licensing requirements.

1.2.1 Microprocessor

•  Dual-core ARM Cortex-A72 MPCore processor and Quad-core ARM Cortex-A53 MPCore processor, both are high-performance, low-power and cached application processors

•  Two CPU clusters. Big cluster with dual-coreCortex-A72 is optimized for high-performance and little cluster with quad-core Cortex-A53 is optimized for low power.

•  Full implementation of the ARM architecture v8-A instruction set, ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerating media and signal processing

•  ARMv8 Cryptography Extensions

•  CCI500 ensures the memory coherency between the two clusters

•  Each Cortex-A72 integrates 48KB L1 instruction cache and 32KB L1 data cache with 4-way set associative. Each Cortex A53 integrates 32KB L1 instruction cache and 32kB L1 data cache separately with 4-way set associative

•  1MB unified L2 Cache for Big cluster, 512KB unified L2 Cache for Little cluster

•  TrustZone technology support

•  Full CoreSight debug solution

•  Debug and trace visibility of whole systems

•  ETM trace support

•  Invasive and non-invasive debug

•  Eight separate power domains for CPU core system to support internal power switch and externally turn on/off based on different application scenario

•  PD_A72_B0: 1st Cortex-A72 + Neon + FPU + L1 I/D cache of big cluster

•  PD_A72_B1: 2nd Cortex-A72+ Neon + FPU + L1 I/D cache of big cluster

•  PD_SCU_B: SCU + L2 Cache controller, and including PD_A72_B0, PD_A72_B1, debug logic of big cluster

•  PD_A53_L0: 1st Cortex-A53 + Neon + FPU + L1 I/D Cache of little cluster

•  PD_A53_L1: 2nd Cortex-A53 + Neon + FPU + L1 I/D Cache of little cluster

•  PD_A53_L2: 3rd Cortex-A53 + Neon + FPU + L1 I/D Cache of little cluster

•  PD_A53_L3: 4th Cortex-A53 + Neon + FPU + L1 I/D Cache of little cluster

•  PD_SCU_L: SCU + L2 Cache controller, and including PD_A53_L0, PD_A53_L1, PD_A53_L2, PD_A53_L3, debug logic of little cluster

•  Two isolated voltage domain to support DVFS for big cluster and little cluster separately

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