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Product Descriptions

RK3288 are low power, high performance processor for mobile phones, personal mobile internet device and other digital multimedia applications, and integrates quad-core CortexA17 with separately NEON coprocessor.

Many embedded powerful hardware engines provide optimized performance for high-end application. RK3288 supports almost full-format; includeH.265 decoder by 2160p@60fps, H.264 decoder by 2160p@24fps, also support H.264/MVC/VP8 encoder by 1080p@30fps, 

high-quality JPEG encoder/decoder, and special image preprocessor and postprocessor.

Embedded 3D GPU makes RK3288 completely compatible with OpenGL ES1.1/2.0/3.0, OpenCL 1.1 and DirectX 11. Special 2D hardware engine with MMU will maximize display performance and provide very smoothly operation.

RK3288 has high-performance dual channel external memory interface (DDR3/DDR3L /LPDDR2/LPDDR3) capable of sustaining demanding memory bandwidth, also provides a complete set of peripheral interface to support very flexible applications.

RK3288 LOT NO# end with “W” is upgraded version, could support HDCP2.2 and USB 1.1.

Product Features

The features listed below which may or may not be present in actual product, may be  subject to the third party licensing requirements. Please contact Rockchip for actual product  feature configurations and licensing requirements.

1.2.1 MicroProcessor

•  Quad-core ARM Cortex-A17 MPCore processor, a high-performance, low-power and cached application processor

•  Full implementation of the ARM architecture v7-A instruction set, ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation

•  Superscalar, variable length, out-of-order pipeline with dynamic branch prediction, 8-stage pipeline 

•  Include VFP v3 hardware to support single and double-precision add, subtract, divide, multiply and accumulate, and square root operations

•  SCU ensures memory coherency between the four CPUs

•  Integrated 32KB L1 instruction cache , 32KB L1 data cache with 4-way set associative

•  1MB unified L2 Cache

•  Trust zone technology support

•  Full coresight debug solution

•  Debug and trace visibility of whole systems

•  ETM trace support

•  Invasive and non-invasive debug

•  Six separate power domains for every core to support internal power switch and externally turn on/off based on different application scenario

•  PD_A17_0: 1st Cortex-A17 + Neon + FPU + L1 I/D Cache

•  PD_A17_1: 2ndCortex-A17 + Neon + FPU + L1 I/D Cache

•  PD_A17_2: 3rdCortex-A17 + Neon + FPU + L1 I/D Cache

•  PD_A17_3: 4thCortex-A17 + Neon + FPU + L1 I/D Cache

•  PD_SCU: SCU + L2 Cache controller, and including PD_A17_0, PD_A17_1, PD_A17_2, PD_A17_3, debug logic

•  One isolated voltage domain to support DVFS

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