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Product Descriptions

RK2818 is a highly-integrated, high-performance, low-power digital multimedia processor which is based on Dual Core (DSP+CPU) architecture with hardware accelerator. It is designed for high-end multimedia product applications such as MID, AP, GPS and Mobile TV etc. 

RK2818 can support decode for various types of video standards such as H.264 /RMVB/MPEG-4/AVS/VC1/MPEG-2 by software and dedicated coprocessors, and encode for some video standards by software. Specially, highest performace for video decode will reach fluent replay for video with H.264 @ 1280x720 formats. RK2818 also provides strong graphics/image ability with embedded GPU. By providing a complete set of peripheral interface, RK2818 can support very flexible applications, including SDRAM/ Mobile SDRAM/DDRII/Mobile DDR, Nor Flash, Nand Flash, LCDC, Sensor, USB OTG 2.0/USB Host 1.0, SD/MMC/SDIO, Wi-Fi, High-speed ADC, I2C, I2S, UART, SPI, PWM etc.

Product Features

•  System Operation

•  Dual Core Architecture (ARM9 + DSP) , including hardware accelerator

•  Support system boot sequentially from ARM to DSP

•  Support address remap function

•  For two cores, all modules have unified address space

•  Selectable JTAG debug method

•  ARM9 debug only (default)

•  DSP debug only

•  ARM9+DSP dual core debug

•  Selectable CPU booting method

•  Boot from NOR Flash

•  Boot from Nand Flash

•  Boot from SPI nor flash

•  Boot from UART device

•  Boot from Host interface

• Memory Organization

•  Internal memory space for ARM processor

•  Internal 16KB SRAM for ARM9 ICache

•  Internal 16KB SRAM for ARM9 DCache

•  Internal 8KB SRAM for ARM9 ITCM

•  Internal 16KB SRAM for ARM9 DTCM

•  Internal memory space for DSP processor

•  Internal 96KB SRAM for DSP Instruction L1 Memory (Also config as 32KB Memory+32KB ICache by software, another 32KB is switched by software)

•  Internal 64KB SRAM for DSP Data L1 Memory

•  Internal 48KB SRAM for DSP Instruction L2 Memory

•  Internal 32KB SRAM for DSP Data L2 Memory

•  Embedded 8KB ROM for CPU Boot

•  Embedded 4KB SRAM for communication between two cores

•  Embedded 48KB SRAM for share among CPU,DSP and LCDC rotator

•  Processors

•  ARM926EJC

•  RISC architecture with 32bit ARM and 16bit Thumb instruction sets

•  Include efficient execution of Java byte codes

•  Built-in MMU to provide flexible memory management needed by many mainstream OS

•  Harvard cached architecture , separate ICache and DCache

•  Separate instruction and data TCM interfaces

•  Separate instruction and data AHB bus interface

•  Support ARM debug architecture
  

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