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   Product Introduction

The PMS152 family is an IO-Type, fully static, OTP-based CMOS 8-bit microcontroller. It employs RISC architecture and all the instructions are executed in one cycle except that some instructions are two cycles that handle indirect memory access.

1.25KW bits OTP program memory and 80 bytes data SRAM are inside, one hardware comparator is built inside the chip to compare signal between two pin or with either internal reference voltage VinternalR or internal bandgap reference voltage. PMS152 also provides three hardware timers: one 16-bit timer, one 8-bit timer with PWM generation, and one new triple 11-bit timer with SuLED PWM generation (LPWMG0, LPWMG1 & LPWMG2) are included.

   Product Features

1.1. Special Features

? General purpose series

? Not supposed to use in AC RC step-down powered or high EFT requirement applications.

PADAUK assumes no liability if such kind of applications can not pass the safety regulation tests.

? Operating temperature range: -40°C ~ 85°C

1.2. System Features

? 1.25KW OTP program memory

? 80 Bytes data RAM

? One hardware 16-bit timer

? One hardware 8-bit timers with 6/7/8-bit PWM generation

? One set triple 11bit SuLED (Super LED) PWM generators and timers

? One hardware comparator

? 14 IO pins with optional pull-high resistor

? Three different IO Driving capability group to meet different application requirements

(1) PB3, PB5, PB7 Drive/ Sink Current= 7mA/30mA

(2) Other IOs (except PA5) Drive/ Sink Current = 7mA/14mA

(3) PA5 Sink Current = 4mA

? Every IO pin can be configured to enable wake-up function

? Clock sources: IHRC, ILRC & EOSC(XTAL mode)

? For every wake-up enabled IO, two optional wake-up speed are supported: normal and fast

? Eight levels of LVR: 4.0V, 3.5V, 3.0V, 2.7V, 2.5V, 2.2V, 2.0V and 1.8V

? Two selectable external interrupt pins: PA0/PB5, PB0/PA4

? Bandgap circuit to provide 1.20V reference voltage

1.3. CPU Features

? One processing unit operating mode

? 86 powerful instructions

? Most instructions are 1T execution cycle

? Programmable stack pointer to provide adjustable stack level

? Direct and indirect addressing modes for data access. Data memories are available for use as an index pointer of Indirect addressing mode

? IO space and memory space are independent

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