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   Product Introduction

The PMS171B family is an ADC-Type, fully static, OTP-based CMOS 8-bit microcontroller. It employs RISC architecture and all the instructions are executed in one cycle except that some instructions are two cycles that handle indirect memory access.

1.5KW OTP program memory and 96 bytes data SRAM are inside, one up to 11 channels 8-bit ADC is built inside the chip with one channel for internal bandgap reference voltage. PMS171B also provides three hardware timers: one is 16-bit timer and two are 8-bit timers with PWM generation. PMS171B also supports one hardware comparator and two super large current outputs.

   Product Features

1.1. Special Features

? General purpose OTP series

? Not supposed to use in AC RC step-down powered or high EFT requirement applications.

PADAUK assumes no liability if such kind of applications can not pass the safety regulation tests.

? Operating temperature range: -20°C ~ 70°C

1.2. System Features

? 1.5KW OTP program memory

? 96 Bytes data RAM

? Clock sources: internal high RC oscillator, internal low RC oscillator and external crystal oscillator

? Bandgap circuit to provide 1.20V reference voltage

? One hardware 16-bit timer

? Two hardware 8-bit timers with PWM generation

? One hardware comparator

? Up to 11-channel 8-bit resolution ADC with one channel comes from bandgap voltage

? Provide ADC reference high voltage: external input, internal VDD

? Eight levels of LVR reset by code option: 4.0V, 3.5V, 3.0V, 2.7V, 2.5V, 2.2V, 2.0V, 1.8V

? Max. 14 IO pins with optional pull-high resistor, two of them with additional pull-low resistor

? PB0 provides NMOS and PB7 provides PMOS super large current output (typ. 125mA@VDD=5.0V)

? Two selectable external interrupt pins by code option

? Every IO pin can be configured to enable wake-up function

? For every wake-up enabled IO, two optional wake-up speed are supported: normal and fast

1.3. CPU Features

? One processing unit operating mode

? 82 powerful instructions

? Most instructions are 1T execution cycle

? Programmable stack pointer to provide adjustable stack level

? Support direct and indirect addressing modes for data access. Data memories are available for use as an index pointer of Indirect addressing mode

? IO space and memory space are independent

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