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Product Descriptions

The 8A34001 Synchronization Management Unit (SMU) provides tools to manage timing references, clock sources, and timing paths for IEEE 1588 and Synchronous Ethernet (SyncE) based clocks. The PLL channels can act independently as frequency synthesizers, jitter attenuators, Digitally Controlled Oscillators (DCO), or Digital Phase Lock Loops (DPLL). Optional clock recovery filter/servo software is available under license from Renesas for use with the 8A34001. The filter/servo software is designed to suppress the effects of Packet Delay Variation (PDV) on packet based timing signals – it can be used with protocol stacks for IEEE 1588 or other packet-based timing protocols. 

Product Typical Applications

? Core and access IP switches/routers

? Synchronous Ethernet equipment

? Telecom Boundary Clocks (T-BCs) and Telecom Time Slave Clocks (T-TSCs) according to ITU-T G.8273.2

? 10Gb, 40Gb, and 100Gb Ethernet interfaces

? Central Office Timing Source and Distribution

? Wireless infrastructure for 4.5G and 5G network equipment

Product Features

? Eight independent timing channels

? Each can act as a frequency synthesizer, jitter attenuator, Digitally Controlled Oscillator (DCO) or Digital Phase Lock Loop (DPLL)

? DPLLs generate telecom compliant clocks 

? Compliant with ITU-T G.8262 for Synchronous Ethernet

? Compliant with legacy SONET/SDH and PDH requirements

? DPLL Digital Loop Filters (DLFs) are programmable with cut off frequencies from 12μHz to 22kHz

? DPLL/DCO channels share frequency information using the Combo Bus to simplify compliance with ITU-T G.8273.2

? Switching between DPLL and DCO modes is hitless and dynamic

? Automatic reference switching between DCO and DPLL modes to simplify support for an external phase/time input interface in a T-BC

? Generates output frequencies that are independent of input frequencies via a Fractional Output Divider (FOD)

? Each FOD supports output phase tuning with 1ps resolution

? 12 Differential / 24 LVCMOS outputs 

? Frequencies from 0.5Hz to 1GHz (250MHz for LVCMOS)

? Jitter below 150fs RMS (10kHz to 20MHz)

? LVCMOS, LVDS, LVPECL, HCSL, CML, SSTL, and HSTL output modes supported

? Differential output swing is selectable: 400mV / 650mV / 800mV / 910mV

? Independent output voltages of 3.3V, 2.5V, or 1.8V

? LVCMOS additionally supports 1.5V or 1.2V

? The clock phase of each output is individually programmable in 1ns to 2ns steps with a total range of ±180°

? 8 differential / 16 single-ended clock inputs

? Supports frequencies from 0.5Hz to 1GHz

? Any input can be mapped to any or all of the timing channels

? Redundant inputs frequency independent of each other

? Any input can be designated as external frame/sync pulse of PPES (pulse per even second), 1PPS (Pulse per Second), 

5PPS, 10PPS, 50Hz, 100Hz, 1 kHz, 2 kHz, 4kHz, and 8kHz associated with a selectable reference clock input

? Per-input programmable phase offset of up to ±1.638?s in 1ps steps

? Reference monitors qualify/disqualify references depending on LOS, activity, frequency monitoring, and/or LOS input pins

? Loss of Signal (LOS) input pins (via GPIOs) can be assigned to any input clock reference

Specifications

Actual product photos

Product Data Book：

For more product information, please download the PDF

Payment&Transportation

Official Certificate&Certificate

Multiple product supply

Company office environment

Warehouse Real Shot

Standard packaging

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